The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a mask read only memory (ROM).
In Patent Document 1 (Japanese Unexamined Patent Application No. HEI 1(1989)-100797, a memory cell is formed by a pair of different MOS transistors. In this memory cell, the fixed data of logic “1” or “0” is programmed based on which one of the pair of MOS transistors is set to a threshold higher than the other transistor. The pair of MOS transistors is coupled to a pair of bit line. The complementary level of the pair of bit lines is given to a differential sense amplifier through a common data line. The differential sense amplifier detects the level difference of the input signal. Then, the differential sense amplifier amplifies the level difference and outputs to the outside as memory cell data.